Analog-devices ADSP-2181 Bedienungsanleitung PDF herunterladen

FUNCTIONAL BLOCK DIAGRAM

DSP Microcomputers

ADSP-2181/ADSP-2183

FEATURES

PERFORMANCE

30 ns Instruction Cycle Time @ 5.0 Volts

33 MIPS Sustained Performance

34.7 ns Instruction Cycle Time @ 3.3 Volts

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 100 Cycle Recovery from

Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator, & Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Zero Overhead Looping

Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory

4 MByte Memory Interface for Storage of Data Tables &

Program Overlays

8-Bit DMA to Byte Memory for Transparent

Program and Data Memory Transfers

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals

Programmable Memory Strobe & Separate I/O Memory

Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

ICE-Port is a trademark of Analog Devices, Inc.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

GENERAL DESCRIPTION

The ADSP-2181/ADSP-2183 is a single-chip microcomputer

optimized for digital signal processing (DSP) and other high

speed numeric processing applications.

The ADSP-2181/ADSP-2183 combines the ADSP-2100 family

base architecture (three computational units, data address gen-

erators and a program sequencer) with two serial ports, a 16-bit

internal DMA port, a byte DMA port, a programmable timer,

Flag I/O, extensive interrupt capabilities, and on-chip program

and data memory.

The ADSP-2181/ADSP-2183 integrates 80K bytes of on-chip

memory configured as 16K words (24-bit) of program RAM,

and 16K words (16-bit) of data RAM. Power down circuitry is

also provided to meet the low power needs of battery operated

portable equipment. The ADSP-2181 is available in 128-pin

TQFP and 128-pin PQFP packages; the ADSP-2183 is avail-

able in the TQFP package only.

In addition, the ADSP-2181/ADSP-2183 supports new instruc-

tions, which include bit manipulations—bit set, bit clear, bit toggle,

bit test—new ALU constants, new multiplication instruction

(x squared), biased rounding, result free ALU operations, I/O memory

transfers, and global interrupt masking, for increased flexibility.

Fabricated in a high speed, double metal, low power, 0.5 µm

CMOS process, the ADSP-2181 operates with a 30 ns instruc-

tion cycle time (34.7 ns for the ADSP-2183). Every instruction

can execute in a single processor cycle.

The ADSP-2181/ADSP-2183’s flexible architecture and com-

prehensive instruction set allow the processor to perform multiple

operations in parallel. In one processor cycle the ADSP-2181/

ADSP-2183 can:

• generate the next program address

• fetch the next instruction

• perform one or two data moves

• update one or two data address pointers

• perform a computational operation

SERIAL PORTS

MEMORY

FLAGS

PROGRAMMABLE

I/O

BYTE DMA

CONTROLLER

PROGRAM

MEMORY

DATA

MEMORY

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

DMA

BUS

INTERNAL

DMA

PORT

TIMER

SPORT 1SPORT 0

ADSP-2100 BASE

ARCHITECTURE

SHIFTER

MAC

ALU

ARITHMETIC UNITS

POWERDOWN

CONTROL

PROGRAM

SEQUENCER

DAG 0

DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

1 2 3 4 5 6 ... 39 40

Inhaltsverzeichnis

Seite 1 - ADSP-2181/ADSP-2183

FUNCTIONAL BLOCK DIAGRAMaDSP MicrocomputersADSP-2181/ADSP-2183FEATURESPERFORMANCE30 ns Instruction Cycle Time @ 5.0 Volts33 MIPS Sustained Performanc

Seite 2

ADSP-2181/ADSP-2183REV. 0–10–If the ADSP-2181/ADSP-2183 is performing an externalmemory access when the external device asserts the BR signal,then it

Seite 3

ADSP-2181/ADSP-2183REV. 0–11–These ADSP-2181/ADSP-2183 pins must be connected only tothe EZ-ICE connector in the target system. These pins have nofunc

Seite 4

ADSP-2181–SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS K Grade B GradeParameter Min Max Min Max UnitVDDSupply Voltage 4.5 5.5 4.5 5.5

Seite 5

ADSP-2181/ADSP-2183REV. 0–13–ESD SENSITIVITYThe ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readilyaccumulat

Seite 6

ADSP-2181/ADSP-2183REV. 0–14–ADSP-2181ENVIRONMENTAL CONDITIONSAmbient Temperature Rating:TAMB = TCASE – (PD × θCA)TCASE = Case Temperature in °CPD = P

Seite 7

ADSP-2181/ADSP-2183REV. 0–15–tDECAY, is dependent on the capacitive load, CL, and the currentload, iL, on the output pin. It can be approximated by th

Seite 8

ADSP-2181/ADSP-2183REV. 0–16–ADSP-2183–SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS K Grade B GradeParameter Min Max Min Max UnitVDDS

Seite 9

ADSP-2181/ADSP-2183REV. 0–17–MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specificationsand the corresponding ADSP-2183 timi

Seite 10

ADSP-2181/ADSP-2183REV. 0–18–(C × VDD2 × f ) is calculated for each output:# ofPins × C × VDD2× fAddress, DMS 8 × 10 pF × 3.32 V × 33.3 MHz = 29.0 mWD

Seite 11

ADSP-2181/ADSP-2183REV. 0–19–ADSP-2183CAPACITIVE LOADINGFigures 17 and 18 show the capacitive loading characteristics ofthe ADSP-2183.CL – pFRISE TIME

Seite 12 - ADSP-2181–SPECIFICATIONS

ADSP-2181/ADSP-2183REV. 0–2–This takes place while the processor continues to:• receive and transmit data through the two serial ports• receive and/or

Seite 13 - WARNING!

ADSP-2181/ADSP-2183REV. 0–20–ADSP-2181Parameter Min Max UnitClock Signals and ResetTiming Requirements:tCKICLKIN Period 60 150 nstCKILCLKIN Width Low

Seite 14

ADSP-2181/ADSP-2183REV. 0–21–ADSP-2181Parameter Min Max UnitInterrupts and FlagTiming Requirements:tIFSIRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3

Seite 15

ADSP-2181/ADSP-2183REV. 0–22–ADSP-2181/ADSP-2183Parameter Min Max UnitBus Request/GrantTiming Requirements:tBHBR Hold after CLKOUT High10.25tCK + 2 ns

Seite 16 - ADSP-2183–SPECIFICATIONS

ADSP-2181/ADSP-2183REV. 0–23–ADSP-2181Parameter Min Max UnitMemory ReadTiming Requirements:tRDDRD Low to Data Valid 0.5tCK – 9 + w nstAAA0-A13, xMS to

Seite 17 - ADSP-2183

ADSP-2181/ADSP-2183REV. 0–24–ADSP-2181/ADSP-2183Parameter Min Max UnitMemory WriteSwitching Characteristics:tDWData Setup before WR High 0.5tCK – 7+ w

Seite 18

ADSP-2181/ADSP-2183REV. 0–25–ADSP-2181/ADSP-2183Parameter Min Max UnitSerial PortsTiming Requirements:tSCKSCLK Period 50 nstSCSDR/TFS/RFS Setup before

Seite 19

ADSP-2181/ADSP-2183REV. 0–26–ADSP-2181/ADSP-2183Parameter Min Max UnitIDMA Address LatchTiming Requirements:tIALPDuration of Address Latch1, 310 nstIA

Seite 20

ADSP-2181/ADSP-2183REV. 0–27–ADSP-2181Parameter Min Max UnitIDMA Write, Short Write CycleTiming Requirements:tIKWIACK Low before Start of Write10nstIW

Seite 21 - ADSP-2181

ADSP-2181/ADSP-2183REV. 0–28–ADSP-2181Parameter Min Max UnitIDMA Write, Long Write CycleTiming Requirements:tIKWIACK Low before Start of Write10nstIKS

Seite 22

ADSP-2181/ADSP-2183REV. 0–29–ADSP-2181Parameter Min Max UnitIDMA Read, Long Read CycleTiming Requirements:tIKRIACK Low before Start of Read10nstIRPDur

Seite 23

ADSP-2181/ADSP-2183REV. 0–3–Program memory can store both instructions and data, permit-ting the ADSP-2181/ADSP-2183 to fetch two operands in asingle

Seite 24

ADSP-2181/ADSP-2183REV. 0–30–ADSP-2181Parameter Min Max UnitIDMA Read, Short Read CycleTiming Requirements:tIKRIACK Low before Start of Read10nstIRPDu

Seite 25

ADSP-2181/ADSP-2183REV. 0–31–128-Lead TQFP Package Pinout6564102IRQL1TFS1/IRQ1RFS1/IRQ010311283938BGEBGBREBRISVDDGNDD23IRDIWRGNDD22D21D20D18D19D17D16D

Seite 26

ADSP-2181/ADSP-2183REV. 0–32–TQFP Pin ConfigurationsTQFP Pin TQFP Pin TQFP Pin TQFP PinNumber Name Number Name Number Name Number Name1 IAL 33 A12 65

Seite 27

ADSP-2181/ADSP-2183REV. 0–33–OUTLINE DIMENSIONS128-Lead Metric Thin Plastic Quad Flatpack (TQFP)656410210311283938 E3 E1 EBe D3 D1 DTOP VIEW(PINS DOWN

Seite 28

ADSP-2181/ADSP-2183REV. 0–34–128-Lead PQFP Package Pinout6564969713332TOP VIEW(PINS DOWN)128L PQFP(28mm x 28mm)128PF1PF2PF3IALBGEBGBREBRISVDDGNDD23IRD

Seite 29

ADSP-2181/ADSP-2183REV. 0–35–PQFP Pin ConfigurationsPQFP Pin PQFP Pin PQFP Pin PQFP PinNumber Name Number Name Number Name Number Name1 PF0 33PWD 65 E

Seite 30

ADSP-2181/ADSP-2183REV. 0–36–OUTLINE DIMENSIONS128-Lead Metric Plastic Quad Flatpack (PQFP)6564969711283332 E3 E1 EBe D3 D1 DTOP VIEW(PINS DOWN)SEATIN

Seite 31

ADSP-2181/ADSP-2183REV. 0–37–ORDERING GUIDEAmbient InstructionTemperature Rate Package PackagePart Number Range (MHz) Description Option*ADSP-2181KST-

Seite 32

–38–

Seite 33

–39–

Seite 34

ADSP-2181/ADSP-2183REV. 0–4–• SPORTs support serial data word lengths from 3 to 16 bitsand provide optional A-law and µ-law companding accordingto CCI

Seite 35

–40–C2144–16–6/96PRINTED IN U.S.A.

Seite 36

ADSP-2181/ADSP-2183REV. 0–5–Table I. Interrupt Priority & Interrupt Vector AddressesInterrupt VectorSource of Interrupt Address (Hex)Reset (or Po

Seite 37

ADSP-2181/ADSP-2183REV. 0–6–When the IDLE (n) instruction is used, it effectively slows downthe processor’s internal clock and thus its response time

Seite 38

ADSP-2181/ADSP-2183REV. 0–7–Table II.PMOVLAY Memory A13 A12:00 Internal Not Applicable Not Applicable1 External 0 13 LSBs of AddressOverlay 1 Between

Seite 39

ADSP-2181/ADSP-2183REV. 0–8–The CMS pin functions like the other memory select signalswith the same timing and bus request logic. A 1 in the enable bi

Seite 40 - PRINTED IN U.S.A

ADSP-2181/ADSP-2183REV. 0–9–Table VI. Boot Summary TableMMAP BMODE Booting Method0 0 BDMA feature is used in default modeto load the first 32 program

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