Analog Devices ADuC812 Bedienungsanleitung

REV. BInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsu

REV. BADuC812–10–OVERVIEW OF MCU-RELATED SFRsAccumulator SFRACC is the Accumulator register and is used for math opera-tions including addition, subtr

REV. BADuC812–11–SPECIAL FUNCTION REGISTERSAll registers except the program counter and the four general purpose register banks, reside in the special

REV. BADuC812–12–ADC CIRCUIT INFORMATIONGeneral OverviewThe ADC conversion block incorporates a fast, 8-channel,12-bit, single supply A/D converter. T

REV. BADuC812–13–ADCCON1 – (ADC Control SFR #1)The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-dow

REV. BADuC812–14–ADCCON2 – (ADC Control SFR #2)The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.SFR Address:

REV. BADuC812–15–Driving the A/D ConverterThe ADC incorporates a successive approximation (SAR) archi-tecture involving a charge-sampled input stage.

REV. BADuC812–16–ground, no amplifier can deliver signals all the way to ground whenpowered by a single supply. Therefore, if a negative supply isavai

REV. BADuC812–17–core. This mode allows the ADuC812 to capture a contiguoussample stream at full ADC update rates (200 kHz).A typical DMA Mode configu

REV. BADuC812–18–the gain calibration coefficient is divided into ADCGAINH (6 bits)and ADCGAINL (8 bits).The offset calibration coefficient compen-sat

REV. BADuC812–19–Using the Flash/EE Program MemoryThis 8K Byte Flash/EE Program Memory array is mappedinto the lower 8K bytes of the 64K bytes program

REV. BADuC812–2–FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1GENERAL DESCRIPTION . . . . . . . . . . .

REV. BADuC812–20–ECON—Flash/EE Memory Control SFRThis SFR acts as a command interpreter and may be writtenwith one of five command modes to enable var

REV. BADuC812–21–USER INTERFACE TO OTHER ON-CHIP ADuC812PERIPHERALSThe following section gives a brief overview of the variousperipherals also availab

REV. BADuC812–22–Using the D/A ConverterThe on-chip D/A converter architecture consists of a resistorstring DAC followed by an output buffer amplifier

REV. BADuC812–23–SOURCE/SINK CURRENT – mA30 5 10 15OUTPUT VOLTAGE – V210Figure 21. Source and Sink Current Capability withVREF = VDD = 3 VTo drive sig

REV. BADuC812–24–WATCHDOG TIMERThe purpose of the watchdog timer is to generate a device resetwithin a reasonable amount of time if the ADuC812 enters

REV. BADuC812–25–POWER SUPPLY MONITORAs its name suggests, the Power Supply Monitor, once enabled,monitors both supplies (AVDD and DVDD) on the ADuC81

REV. BADuC812–26–SERIAL PERIPHERAL INTERFACEThe ADuC812 integrates a complete hardware Serial PeripheralInterface (SPI) on-chip. SPI is an industry st

REV. BADuC812–27–Table XII. SPICON SFR Bit Designations (continued)Bit Name Description1 SPR1 SPI Bit-Rate Select Bits.0 SPR0 These bits select the SC

REV. BADuC812–28–I2C-COMPATIBLE INTERFACEThe ADuC812 supports a 2-wire serial interface mode which isI2C compatible. The I2C-compatible interface shar

REV. BADuC812–29–8051-COMPATIBLE ON-CHIP PERIPHERALSThis section gives a brief overview of the various secondaryperipheral circuits that are also avai

REV. B–3–ADuC812 ADuC812BSParameter VDD = 5 V VDD = 3 V Unit Test Conditions/CommentsADC CHANNEL SPECIFICATIONSDC ACCURACY3, 4Resolution 12

REV. BADuC812–30–User configuration and control of all Timer operating modes isachieved via three SFRs, namely:TMOD, TCON: Control and configuration f

REV. BADuC812–31–1FT1RT0FT0RT1EI11TI10EI10TI1NOTE1These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control

REV. BADuC812–32–Mode 2 (8-Bit Timer/Counter with Auto Reload)Mode 2 configures the timer register as an 8-bit counter (TL0)with automatic reload, as

REV. BADuC812–33–T2CON Timer/Counter 2 Control RegisterSFR Address C8HPower-On Default Value 00HBit Addressable Yes2FT2FXEKLCRKLCT2NEXE2RT2TNC2PACTabl

REV. BADuC812–34–Timer/Counter Operation ModesThe following paragraphs describe the operating modes for timer/counter 2. The operating modes are selec

REV. BADuC812–35–UART SERIAL INTERFACEThe serial port is full duplex, meaning it can transmit and receivesimultaneously. It is also receive-buffered,

REV. BADuC812–36–Mode 0: 8-Bit Shift Register ModeMode 0 is selected by clearing both the SM0 and SM1 bits in theSFR SCON. Serial data enters and exit

REV. BADuC812–37–Timer 1 Generated Baud RatesWhen Timer 1 is used as the baud rate generator, the baud ratesin Modes 1 and 3 are determined by the Tim

REV. BADuC812–38–INTERRUPT SYSTEMThe ADuC812 provides a total of nine interrupt sources withtwo priority levels. The control and configuration of the

REV. BADuC812–39–IE2: Secondary Interrupt Enable RegisterSFR Address A9HPower-On Default Value 00HBit Addressable No—————— IMSPEISETable XXV. IE2 SFR

REV. B–4–ADuC812–SPECIFICATIONS1, 2 ADuC812BSParameter VDD = 5 V VDD = 3 V Unit Test Conditions/CommentsDAC AC CHARACTERISTICSVoltage Outpu

REV. BADuC812–40–ADuC812 HARDWARE DESIGN CONSIDERATIONSThis section outlines some of the key hardware design consider-ations that must be addressed wh

REV. BADuC812–41–If access to more than 64K bytes of RAM is desired, a featureunique to the ADuC812 allows addressing up to 16M bytesof external RAM s

REV. BADuC812–42–As an alternative to providing two separate power supplies, theuser can help keep AVDD quiet by placing a small series resistorand/or

REV. BADuC812–43–Grounding and Board Layout RecommendationsAs with all high resolution data converters, special attention mustbe paid to grounding and

REV. BADuC812–44–C1+V+C1–C2+C2–V–T2OUTR2INVCCGNDT1OUTR1INR1OUTT1INT2INR2OUTADM202DVDD2734333130292839383736353240474644434241525150494845DVDD1kDVDD1k

REV. BADuC812–45–Note that the serial port debugger is fully contained on theADuC812 device, (unlike “ROM monitor” type debuggers) andtherefore no ext

REV. BADuC812–46–(AVDD = DVDD = 3.0 V or 5.0 V  10%. All specifications TA = TMIN to TMAX unless otherwise noted.) 12 MHz Variable ClockParam

REV. BADuC812–47– 12 MHz Variable ClockParameter Min Max Min Max Unit FigureEXTERNAL PROGRAM MEMORYtLHLLALE Pulsewidth 127 2tCK–40 ns 52tAVLL

REV. BADuC812–48– 12 MHz Variable ClockParameter Min Max Min Max Unit FigureEXTERNAL DATA MEMORY READ CYCLEtRLRHRD Pulsewidth 400 6tCK– 100 ns 5

REV. BADuC812–49– 12 MHz Variable ClockParameter Min Max Min Max Unit FigureEXTERNAL DATA MEMORY WRITE CYCLEtWLWHWR Pulsewidth 400 6tCK– 100 ns

REV. B–5–ADuC812 ADuC812BSParameter VDD = 5 V VDD = 3 V Unit Test Conditions/CommentsDIGITAL OUTPUTSOutput High Voltage (VOH) 2.4 V min VDD

REV. BADuC812–50– 12 MHz Variable ClockParameter Min Typ Max Min Typ Max Unit FigureUART TIMING (Shift Register Mode)tXLXLSerial Port Clock Cyc

REV. BADuC812–51–Parameter Min Max Unit FigureI2C-COMPATIBLE INTERFACE TIMINGtLSCLOCK Low Pulsewidth 4.7 µs56tHSCLOCK High Pulsewidth 4.0 µs56tSHDStar

REV. BADuC812–52–Parameter Min Typ Max Unit FigureSPI MASTER MODE TIMING (CPHA = 1)tSLSCLOCK Low Pulsewidth 330 ns 57tSHSCLOCK High Pulsewidth 330 ns

REV. BADuC812–53–Parameter Min Typ Max Unit FigureSPI MASTER MODE TIMING (CPHA = 0)tSLSCLOCK Low Pulsewidth 330 ns 58tSHSCLOCK High Pulsewidth 330 ns

REV. BADuC812–54–Parameter Min Typ Max Unit FigureSPI SLAVE MODE TIMING (CPHA = 1)tSSSS to SCLOCK Edge 0 ns 59tSLSCLOCK Low Pulsewidth 330 ns 59tSHSCL

REV. BADuC812–55–Parameter Min Typ Max Unit FigureSPI SLAVE MODE TIMING (CPHA = 0)tSSSS to SCLOCK Edge 0 ns 60tSLSCLOCK Low Pulsewidth 330 ns 60tSHSCL

REV. B–56–C00208–0–10/01(B)PRINTED IN U.S.A.ADuC812OUTLINE DIMENSIONSDimensions shown in inches and (mm).52-Lead Plastic Quad Flatpack(S-52)TOP VIEW(P

REV. BADuC812–6–PIN CONFIGURATION52 51 50 49 48 43 42 41 4047 46 45 4414 15 16 17 18 19 20 21 22 23 24 25 26123456789101312113938373635343332313029282

REV. BADuC812–7–PIN FUNCTION DESCRIPTIONSMnemonic Type FunctionDVDDP Digital Positive Supply Voltage, 3 V or 5 V NominalAVDDP Analog Positive Supply V

REV. BADuC812–8–Mnemonic Type FunctionPSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external programmemo

REV. BADuC812–9–ARCHITECTURE, MAIN FEATURESThe ADuC812 is a highly integrated true 12-bit data acquisitionsystem. At its core, the ADuC812 incorporate