Analog-devices TigerSHARC ADSP-TS201S Bedienungsanleitung

•aTigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.TigerSHARC®Embedded ProcessorADSP-TS201SRev. CInformation furnis

Rev. C | Page 10 of 48 | December 2006ADSP-TS201SPOWER DOMAINSThe ADSP-TS201S processor has separate power supply con-nections for internal logic (VDD

ADSP-TS201SRev. C | Page 11 of 48 | December 2006eliminating the need to start from the very beginning when developing new application code. The VDK f

Rev. C | Page 12 of 48 | December 2006ADSP-TS201SPIN FUNCTION DESCRIPTIONSWhile most of the ADSP-TS201S processor’s input pins are nor-mally synchrono

ADSP-TS201SRev. C | Page 13 of 48 | December 2006Table 5. Pin Definitions—External Port Bus Controls Signal Type Term DescriptionADDR31–0 I/O/T(pu_ad)

Rev. C | Page 14 of 48 | December 2006ADSP-TS201STable 6. Pin Definitions—External Port Arbitration Signal Type Term DescriptionBR7–0I/O VDD_IO1Multip

ADSP-TS201SRev. C | Page 15 of 48 | December 2006Table 7. Pin Definitions—External Port DMA/Flyby Signal Type Term DescriptionDMAR3–0I/A epu DMA Reque

Rev. C | Page 16 of 48 | December 2006ADSP-TS201STable 8. Pin Definitions—External Port SDRAM Controller Signal Type Term DescriptionMSSD3–0I/O/T(pu_0

ADSP-TS201SRev. C | Page 17 of 48 | December 2006Table 9. Pin Definitions—JTAG Port Signal Type Term DescriptionEMUO/OD nc1Emulation. Connected to the

Rev. C | Page 18 of 48 | December 2006ADSP-TS201STable 11. Pin Definitions—Link Ports Signal Type Term DescriptionLxDATO3–0P O nc Link Ports 3–0 Data

ADSP-TS201SRev. C | Page 19 of 48 | December 2006Table 13. Impedance Control SelectionCONTROLIMP1-0 Driver Mode00 (recommended) Normal 01 Reserved10 (

Rev. C | Page 2 of 48 | December 2006ADSP-TS201STABLE OF CONTENTSGeneral Description ... 3Dual Compute

Rev. C | Page 20 of 48 | December 2006ADSP-TS201SSTRAP PIN FUNCTION DESCRIPTIONSSome pins have alternate functions at reset. Strap options set DSP ope

ADSP-TS201SRev. C | Page 21 of 48 | December 2006ADSP-TS201S—SPECIFICATIONSNote that component specifications are subject to change with-out notice. F

Rev. C | Page 22 of 48 | December 2006ADSP-TS201SELECTRICAL CHARACTERISTICSTable 18. Maximum Duty Cycle for Input Transient VoltageVIN Max (V)1VIN Min

ADSP-TS201SRev. C | Page 23 of 48 | December 2006PACKAGE INFORMATIONThe information presented in Figure 8 provide details about the package branding f

Rev. C | Page 24 of 48 | December 2006ADSP-TS201STIMING SPECIFICATIONSWith the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all

ADSP-TS201SRev. C | Page 25 of 48 | December 2006Table 23. Reference Clocks—System Clock (SCLK) Cycle TimeParameter DescriptionSCLKRAT = 4×, 6×, 8×, 1

Rev. C | Page 26 of 48 | December 2006ADSP-TS201STable 25. Power-Up Timing1Parameter Min Max UnitTiming RequirementtVDD_DRAMVDD_DRAM Stable After VDD,

ADSP-TS201SRev. C | Page 27 of 48 | December 2006Table 27. Normal Reset TimingParameter Min Max UnitTiming RequirementstRST_INRST_IN Asserted 2 mstSTR

Rev. C | Page 28 of 48 | December 2006ADSP-TS201STable 29. AC Signal Specifications (All values in this table are in nanoseconds.)Name DescriptionInpu

ADSP-TS201SRev. C | Page 29 of 48 | December 2006DS2–08Static Pins—Must Be Constant — — — — — — —SCLKRAT2–08Static Pins—Must Be Constant — — — — — — —

ADSP-TS201SRev. C | Page 3 of 48 | December 2006GENERAL DESCRIPTIONThe ADSP-TS201S TigerSHARC processor is an ultrahigh per-formance, static superscal

Rev. C | Page 30 of 48 | December 2006ADSP-TS201SLink Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and TimingTable 30 and

ADSP-TS201SRev. C | Page 31 of 48 | December 2006Link Port—Data Out TimingTable 32 with Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, and Fig

Rev. C | Page 32 of 48 | December 2006ADSP-TS201SFigure 18. Link Ports—Output ClockFigure 19. Link Ports—Differential Output Signals Transition TimeLx

ADSP-TS201SRev. C | Page 33 of 48 | December 2006Figure 22. Link Ports—Transmission End and StopsFigure 23. Link Ports—Back to Back TransmissionLxCLKO

Rev. C | Page 34 of 48 | December 2006ADSP-TS201SLink Port—Data In TimingTable 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS

ADSP-TS201SRev. C | Page 35 of 48 | December 2006Figure 25. Link Ports—Data Input Setup and Hold11These parameters are valid for both clock edges.LxCL

Rev. C | Page 36 of 48 | December 2006ADSP-TS201SOUTPUT DRIVE CURRENTSFigure 26 through Figure 33 show typical I–V characteristics for the output driv

ADSP-TS201SRev. C | Page 37 of 48 | December 2006TEST CONDITIONSThe ac signal specifications (timing parameters) appear in Table 29 on Page 28. These

Rev. C | Page 38 of 48 | December 2006ADSP-TS201SOutput Enable TimeOutput pins are considered to be enabled when they have made a transition from a hi

ADSP-TS201SRev. C | Page 39 of 48 | December 2006Figure 41. Typical Output Rise and Fall Time (10% to 90%, VDD_IO=2.5V) vs. Load Capacitance at Streng

Rev. C | Page 4 of 48 | December 2006ADSP-TS201SThe TigerSHARC DSP uses a Static SuperscalarTM† architecture. This architecture is superscalar in that

Rev. C | Page 40 of 48 | December 2006ADSP-TS201SENVIRONMENTAL CONDITIONSThe ADSP-TS201S processor is rated for performance under TCASE environmental

ADSP-TS201SRev. C | Page 41 of 48 | December 2006576-BALL BGA_ED PIN CONFIGURATIONS Figure 46 shows a summary of pin configurations for the 576-ball B

Rev. C | Page 42 of 48 | December 2006ADSP-TS201STable 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments Ball No. Signal Name Ball No. Signal Name

ADSP-TS201SRev. C | Page 43 of 48 | December 2006J1 RAS K1 SDA10 L1 SDWE M1 BR3J2 CAS K2 SDCKE L2 BR0 M2 SCLKRAT1J3 VSSK3 LDQM L3 BR1 M3 BR5J4 VREFK4

Rev. C | Page 44 of 48 | December 2006ADSP-TS201SU1 MSSD0 V1 MSSD2 W1 CONTROLIMP0 Y1 EMUU2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCKU3 ID2 V3 POR_IN W3 TDI Y3

ADSP-TS201SRev. C | Page 45 of 48 | December 2006OUTLINE DIMENSIONSThe ADSP-TS201S processor is available in a 25 mm × 25 mm, 576-ball metric thermall

Rev. C | Page 46 of 48 | December 2006ADSP-TS201SORDERING GUIDEModelTemperature Range11Represents case temperature.InstructionRate22The instruction ra

ADSP-TS201SRev. C | Page 47 of 48 | December 2006

Rev. C | Page 48 of 48 | December 2006ADSP-TS201S©2006 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property

ADSP-TS201SRev. C | Page 5 of 48 | December 2006The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular

Rev. C | Page 6 of 48 | December 2006ADSP-TS201S33.6G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit in

ADSP-TS201SRev. C | Page 7 of 48 | December 2006The ADSP-TS201S processor provides programmable memory, pipeline depth, and idle cycle for synchronous

Rev. C | Page 8 of 48 | December 2006ADSP-TS201Sexternal memory. These transfers only use handshake mode protocol. DMA priority rotates between the fo

ADSP-TS201SRev. C | Page 9 of 48 | December 2006LINK PORTS (LVDS)The DSP’s four full-duplex link ports each provide additional four-bit receive and fo